Measurement of SRAM Power-Up State for PUF Applications using an Addressable SRAM Cell Array Test Structure

被引:0
|
作者
Takeuchi, Kiyoshi [1 ]
Mizutani, Tomoko [1 ]
Saraya, Takuya [1 ]
Kobayashi, Masaharu [1 ]
Hiramoto, Toshiro [1 ]
Shinohara, Hirofumi [2 ]
机构
[1] Univ Tokyo, Inst Ind Sci, Tokyo, Japan
[2] Waseda Univ, Grad Sch Informat Prod & Syst, Fukuoka, Japan
关键词
test structure; physical unclonable function; SRAM;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
SRAM data just after power-up were measured using an addressable SRAM cell array test structure. It was found that the results are strongly affected by the address switching noise and "memory effect". An addressing sequence combined with word line reset pulse application is proposed for reliable power-up data stability evaluation.
引用
收藏
页码:130 / 134
页数:5
相关论文
共 25 条
  • [11] SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram
    Torrens, Gabriel
    Alheyasat, Abdel
    Alorda, Bartomeu
    Bota, Sebastia A.
    ELECTRONICS, 2022, 11 (01)
  • [12] Design of SRAM Array Using 8T Cell for Low Power Sensor Network
    Karat, Colin David
    Krishna, Soorya K.
    2015 5TH NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE), 2015,
  • [13] Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications
    Jitendra Kumar Mishra
    Bharat Bhushan Upadhyay
    Prasanna Kumar Misra
    Manish Goswami
    Circuits, Systems, and Signal Processing, 2021, 40 : 2135 - 2158
  • [14] Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications
    Mishra, Jitendra Kumar
    Upadhyay, Bharat Bhushan
    Misra, Prasanna Kumar
    Goswami, Manish
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2021, 40 (05) : 2135 - 2158
  • [15] Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications
    Mishra, Jitendra Kumar
    Misra, Prasanna Kumar
    Goswami, Manish
    APCCAS 2020: PROCEEDINGS OF THE 2020 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2020), 2020, : 50 - 53
  • [16] A 4x4 modified 8 T SRAM cell array using power gating technique
    Saranya, L.
    Arvind, C.
    Karthigaikumar, P.
    Balachander, K.
    MATERIALS TODAY-PROCEEDINGS, 2021, 45 : 1820 - 1826
  • [17] Comparison of 6T-SRAM Cell Designs using DTMOS and VTMOS for Low Power Applications
    Sharan, Sneha
    Chandra, Anshu
    Goel, Nidhi
    Kumar, Ashwani
    PROCEEDINGS OF THE FIRST IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, INTELLIGENT CONTROL AND ENERGY SYSTEMS (ICPEICES 2016), 2016,
  • [18] Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array
    Hiramoto, Toshiro
    Suzuki, Makoto
    Song, Xiaowei
    Shimizu, Ken
    Saraya, Takuya
    Nishida, Akio
    Tsunomura, Takaaki
    Kamohara, Shiro
    Takeuchi, Kiyoshi
    Mogami, Tohru
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (08) : 2249 - 2256
  • [19] Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell
    Shalini Singh
    Shyam Akashe
    Wireless Personal Communications, 2017, 96 : 1099 - 1109
  • [20] Low Power Consuming 1 KB (32 x 32) Memory Array Using Compact 7T SRAM Cell
    Singh, Shalini
    Akashe, Shyam
    WIRELESS PERSONAL COMMUNICATIONS, 2017, 96 (01) : 1099 - 1109