Measurement of SRAM Power-Up State for PUF Applications using an Addressable SRAM Cell Array Test Structure

被引：0

作者：

Takeuchi, Kiyoshi ^{[1
]}

Mizutani, Tomoko ^{[1
]}

Saraya, Takuya ^{[1
]}

Kobayashi, Masaharu ^{[1
]}

Hiramoto, Toshiro ^{[1
]}

Shinohara, Hirofumi ^{[2
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Tokyo, Japan

[2] Waseda Univ, Grad Sch Informat Prod & Syst, Fukuoka, Japan

来源：

2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) | 2016年

关键词：

test structure; physical unclonable function; SRAM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

SRAM data just after power-up were measured using an addressable SRAM cell array test structure. It was found that the results are strongly affected by the address switching noise and "memory effect". An addressing sequence combined with word line reset pulse application is proposed for reliable power-up data stability evaluation.

引用

页码：130 / 134

页数：5

共 24 条

[1] Power-up control techniques for reliable SRAM PUF
Lee, Juyun
Jee, Dong-Woo
Jeon, Dongsuk
[J]. IEICE ELECTRONICS EXPRESS, 2019, 16 (13):
[2] Measurement of Static Random Access Memory Power-Up State Using an Addressable Cell Array Test Structure
Takeuchi, Kiyoshi
Mizutani, Tomoko
Shinohara, Hirofumi
Saraya, Takuya
Kobayashi, Masaharu
Hiramoto, Toshiro
[J]. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2017, 30 (03) : 209 - 215
[3] The Cell Dependency Analysis on Learning SRAM Power-Up States
Liao, Zhonghao
Guan, Yong
[J]. PROCEEDINGS OF THE 2018 ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST), 2018, : 37 - 43
[4] Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Holcomb, Daniel E.
Burleson, Wayne P.
Fu, Kevin
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2009, 58 (09) : 1198 - 1210
[5] A study of variation in characteristics and subthreshold humps for 65-nm SRAM using newly developed SRAM cell array test structure
Mizumura, A.
Suzuki, T.
Arima, T.
Maeda, H.
Ammo, H.
[J]. 2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS, 2008, : 8 - +
[6] Design of SRAM Cell using FinFET for Low Power Applications
Vajeer, Shruthi
Vallab, Lavanya
Yada, Pravalika
Vallem, Sharmila
[J]. 2024 7TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS, ICDCS 2024, 2024, : 243 - 247
[7] Using Power-Up SRAM State of Atmel ATmega1284P Microcontrollers as Physical Unclonable Function for Key Generation and Chip Identification
Platonov, Mikhail
Hlavac, Josef
Lorencz, Robert
[J]. INFORMATION SECURITY JOURNAL, 2013, 22 (5-6): : 244 - 250
[8] Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis
K. Gavaskar
P. Sivaranjani
S. Elango
G. Nirmal Raja
[J]. Wireless Personal Communications, 2023, 129 : 37 - 55
[9] Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis
Gavaskar, K.
Sivaranjani, P.
Elango, S.
Raja, G. Nirmal
[J]. WIRELESS PERSONAL COMMUNICATIONS, 2023, 129 (01) : 37 - 55
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