Design and implementation of the PAPRICA parallel architecture

被引:8
|
作者
Broggi, A [1 ]
Conte, G
Gregoretti, F
Sansoe, C
Passerone, R
Reyneri, LM
机构
[1] Univ Parma, Dipartimento Ingn Informaz, I-43100 Parma, Italy
[2] Politecn Torino, Dipartimento Elettron, Turin, Italy
关键词
IEEE Computer Society; Mathematical Morphology; Computational Paradigm; Graphic Operator; Road Detection;
D O I
10.1023/A:1008095714465
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper PAPRICA, a massively parallel coprocessor devoted to the analysis of bitmapped images is presented considering first the computational model, then the architecture and its implementation, and finally the performance analysis. The main goal of the project was to develop a subsystem to be attached to a standard workstation and to operate as a specialized processing module in dedicated systems. The computational model is strongly related to the concepts of mathematical morphology, and therefore the instruction set of the processing units implements basic morphological transformations. Moreover, the specific processor virtualization mechanism allows to handle and process multiresolution data sets. The actual implementation consists of a mesh of 256 single bit processing units operating in a SIMD style and is based on a set of custom VLSI circuits. The architecture comprises specific hardware extensions that significantly improved performances in real-time applications.
引用
收藏
页码:5 / 18
页数:14
相关论文
共 50 条
  • [31] Data flow architecture for the parallel implementation of the functional language
    Jelsina, M
    Krahulik, P
    Legnavsky, M
    [J]. ICICS - PROCEEDINGS OF 1997 INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATIONS AND SIGNAL PROCESSING, VOLS 1-3: THEME: TRENDS IN INFORMATION SYSTEMS ENGINEERING AND WIRELESS MULTIMEDIA COMMUNICATIONS, 1997, : 1452 - 1456
  • [32] Design and Implementation of Texture Mapping in Parallel
    Xu, Wen
    Han, Jungang
    [J]. PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON ELECTRIC AND ELECTRONICS, 2013, : 86 - 89
  • [33] Implementation of parallel adder using combinatorial logic architecture
    Yarning Wu
    [J]. Chinese Journal of Lasers, 1992, (04) : 81 - 86
  • [34] Fast, parallel implementation of particle filtering on the GPU architecture
    Anna Gelencsér-Horváth
    Gábor János Tornai
    András Horváth
    György Cserey
    [J]. EURASIP Journal on Advances in Signal Processing, 2013
  • [35] A parallel architecture for implementation of filters based on order statistics
    Gasteratos, A
    Andreadis, I
    Tsalides, P
    [J]. PATTERN RECOGNITION LETTERS, 1998, 19 (09) : 815 - 820
  • [36] Hough transform implementation on a reconfigurable highly parallel architecture
    Mahmoud, M
    Nakanishi, M
    Ogura, T
    [J]. CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS, 1997, : 186 - 194
  • [37] Design and implementation of a parallel crypto server
    Rong, XF
    Gao, XJ
    Su, RD
    Zhou, LH
    [J]. COMPUTATIONAL INTELLIGENCE AND SECURITY, PT 2, PROCEEDINGS, 2005, 3802 : 398 - 406
  • [38] Design and Implementation of Parallel Pipeline Processor
    Fan, Hongyu
    Zhang, Hui
    Jiang, Nan
    Guo, Dongwei
    [J]. PROCEEDINGS OF THE 2017 2ND INTERNATIONAL CONFERENCE ON MATERIALS SCIENCE, MACHINERY AND ENERGY ENGINEERING (MSMEE 2017), 2017, 123 : 370 - 374
  • [39] Design and Implementation of a Massively Parallel ESB
    Benosman, Ridha
    Barkaoui, Kamel
    Albrieux, Yves
    [J]. 2013 11TH INTERNATIONAL SYMPOSIUM ON PROGRAMMING AND SYSTEMS (ISPS), 2013, : 89 - 95
  • [40] Design and Implementation of Parallel FFT on CUDA
    Zhang, Xueqin
    Shen, Kai
    Xu, Chengguang
    Wang, Kaifang
    [J]. 2013 IEEE 11TH INTERNATIONAL CONFERENCE ON DEPENDABLE, AUTONOMIC AND SECURE COMPUTING (DASC), 2013, : 583 - 589