Equivalent circuit model of ESD protection devices

In this paper, we propose an equivalent circuit model that describes the snapback characteristics of ESD (ElectroStatic Discharge) protection devices constructed using MOS transistors. Our goal was to predict the ESD immunity of CMOS integrated circuits using circuit simulations. The ESD immunity can be predicted from the high-current behavior (the snapback characteristics) of the protection devices. In this paper, we explain our equivalent circuit model, which includes a parasitic bipolar transistor with a generated-hole-dependent base resistance. Because the models for parasitic elements are combined with a SPICE MOS transistor model, our model can represent the gate bias dependence of snapback characteristics. The equivalent circuit parameters are extracted from the device simulations and modified to reproduce the measured snapback characteristics of the MOS transistor. Therefore, our equivalent circuit model for MOS protection devices can be used in ESD circuit simulations.