An Efficient FPGA Architectu re for Hardware Realization of Hexagonal Based Motion Estimation Algorithm

被引：0

作者：

Muzammil, M. ^{[1
]}

Ali, I. ^{[2
]}

Sharif, M. ^{[3
]}

Khalil K, A. ^{[4
]}

机构：

[1] Int Islamic Univ, Islamabad 47000, Pakistan

[2] Natl Ctr Phys, Islamabad 47000, Pakistan

[3] Univ Engn & Technol, Taxila 47070, Pakistan

[4] Univ Engn & Technol, Taxila 47070, Pakistan

来源：

2015 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Motion Estimation (ME) is the most critical and complex part of any video codec system. The different algorithms and their architectures are proposed for ME process. In this paper, we have proposed an efficient architecture for Hexagon Based Search (HexBS) algorithm and implemented on XC4VSX25 Virtex4 FPGA. Simulation results show that the proposed architecture is capable of calculating the Motion Vectors (MVs) of 1280 x 720 High Definition (HD) videos with the best case throughput of 70 frames/sec. Moreover, the power and frequency requirements are 215mW and 127.27 MHz respectively for the proposed architecture with minimum hardware resources. Hence the proposed architecture is suitable for the real-time HD video applications.

引用

页码：422 / 423

页数：2

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