An improved CMOS offset-compensated current comparator for high speed applications

被引：0

作者：

Worapishet, A ^{[1
]}

Hughes, JB ^{[1
]}

Toumazou, C ^{[1
]}

机构：

[1] Mahanakorn Univ Technol, Dept Elect Engn, Bangkok, Thailand

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

An improved CMOS current comparator suitable for use with either (SI)-I-2 or (SI)-I-3 switched-current cells is presented in this paper. The circuit also incorporates new design techniques to enhance both speed and resolution. A practical CMOS design is presented and simulations show operation at 80 MHz with 10 bit precision from a 3 V supply.

引用

页码：535 / 538

页数：4

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