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- [4] Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3D IC Packaging IPACK 2009: PROCEEDINGS OF THE ASME INTERPACK CONFERENCE 2009, VOL 1, 2010, : 67 - 74
- [5] Thermal Stress Analysis and Design Guidelines for Through Silicon Via Structure in 3D IC Integration 2018 19TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2018, : 883 - 885
- [6] Thermal aware Graphene Based Through Silicon Via Design for 3D IC 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
- [7] Thermal performance of 3D IC integration with Through-Silicon Via (TSV) Chien, H.-C. (Jack_Chien@itri.org.tw), 1600, IMAPS-International Microelectronics and Packaging Society (09):
- [8] Stress Analysis in 3D IC having Thermal Through Silicon Vias (TTSV) 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2337 - 2341
- [9] 3D Stacked IC Demonstration using a Through Silicon Via First Approach IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 603 - +