共 50 条
- [1] MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (03): : 429 - 436
- [3] MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process 2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2003, : 84 - 87
- [4] MOS INTEGRATED CIRCUITS: IMPROVEMENTS OF THEIR ESD PROTECTION. RGE, Revue Generale de l'Electricite, 1987, (02): : 25 - 28
- [7] Analysis of ESD Protection Circuits for High - Performance CMOS Structures PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE AND EXPOSITION ON ELECTRICAL AND POWER ENGINEERING (EPE 2012), 2012, : 713 - 716
- [8] Novel Gate-Voltage-Bias Techniques for Gate-Coupled MOS (GCMOS) ESD Protection Circuits 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
- [9] Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2001, : 91 - 96
- [10] ESD protection for BiCMOS circuits PROCEEDINGS OF THE 2000 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2000, : 218 - 221