PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

被引：17

作者：

Miettinen, Pekka ^{[1
]}

Honkala, Mikko ^{[1
]}

Roos, Janne ^{[2
]}

Valtonen, Martti ^{[1
]}

机构：

[1] Aalto Univ, Sch Elect Engn, Dept Radio Sci & Engn, FI-00076 Aalto, Finland

[2] AWR APLAC Corp, FI-02600 Espoo, Finland

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2011年 / 30卷 / 03期

基金：

芬兰科学院;

关键词：

Circuit simulation; interconnect modeling; model-order reduction; RLC circuits;

D O I：

10.1109/TCAD.2010.2090751

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the reduction. As the method produces a positive-valued, passive, and stable reduced-order RLC circuit (netlist-in-netlist-out), it can be used in conjunction with any standard analysis tool or circuit simulator without modification. It is shown that PartMOR achieves excellent reduction results in terms of accuracy and reduced CPU time for RLC, RC, and RL circuits.

引用

页码：374 / 387

页数：14

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