An Enhanced Floating Gate Memory for the Online Training of Analog Neural Networks

被引:1
|
作者
Gan, Lurong [1 ]
Wang, Chen [1 ]
Chen, Lin [1 ]
Zhu, Hao [1 ]
Sun, Qingqing [1 ]
Zhang, David Wei [1 ]
机构
[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
关键词
Neural network; FG memory; U-shaped channel; erasing speed; online training; SYNAPSES;
D O I
10.1109/JEDS.2020.2964820
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Floating gate (FG) memory has long erasing time, which limits its application as an electronic synapse in online training. This paper proposes a novel enhanced floating gate memory (EFM) by TCAD simulation. Here, three other structures are simulated just for comparison. The simulation results show that the erasing speed is about 34ns while the other three need the time over 1.8ms, which makes the operation speed of long-term potentiation (LTP) more symmetrical to long-term depression (LTD). In addition, both LTP and LTD are approximately linear in the simulation results. The speed, linearity, and symmetry of weight update are the keys to online training of analog neural networks. These excellent performances indicated a potential application of EFM in analog neuro-inspired computing.
引用
收藏
页码:84 / 91
页数:8
相关论文
共 50 条
  • [31] Characterization of floating gate defects in analog cells
    Brosa, AM
    Figueras, J
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 14 (1-2): : 23 - 31
  • [32] Characterization of Floating Gate Defects in Analog Cells
    Anna M. Brosa
    Joan Figueras
    Journal of Electronic Testing, 1999, 14 : 23 - 31
  • [33] Neural Networks Implicated in Autobiographical Memory Training
    Cirneci, Dragos
    Onu, Mihaela
    Papasteri, Claudiu C.
    Georgescu, Dana
    Poalelungi, Catalina
    Sofonea, Alexandra
    Puscasu, Nicoleta
    Tanase, Dumitru
    Radeanu, Teofila
    Toader, Maria-Yaelle
    Dogaru, Andreea L.
    Podina, Ioana R.
    Berceanu, Alexandru I.
    Carcea, Ioana
    ENEURO, 2022, 9 (06)
  • [34] A CMOS programmable analog memory-cell array using floating-gate circuits
    Harrison, RR
    Bragg, JA
    Hasler, P
    Minch, BA
    Deweerth, SP
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2001, 48 (01) : 4 - 11
  • [35] LOW PROGRAMMING VOLTAGE FLOATING GATE ANALOG MEMORY CELLS IN STANDARD VLSI CMOS TECHNOLOGY
    DURFEE, DA
    SHOUCAIR, FS
    ELECTRONICS LETTERS, 1992, 28 (10) : 925 - 927
  • [36] Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays
    Rumberg, Brandon
    Clites, Spencer
    Abulaiha, Haifa
    DiLello, Alexander
    Graham, David
    JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2021, 11 (01) : 1 - 21
  • [37] REVERSIBLE FLOATING-GATE MEMORY
    CARD, HC
    WORRALL, AG
    JOURNAL OF APPLIED PHYSICS, 1973, 44 (05) : 2326 - 2330
  • [38] Floating gate memory paper transistor
    Martins, R.
    Pereira, L.
    Barquinha, P.
    Correia, N.
    Goncalves, G.
    Ferreira, I.
    Dias, C.
    Fortunato, E.
    OXIDE-BASED MATERIALS AND DEVICES, 2010, 7603
  • [39] Photonic Long-Short Term Memory Neural Networks with Analog Memory
    Howard, Emma R.
    Marquez, Bicky A.
    Shastri, Bhavin J.
    2020 IEEE PHOTONICS CONFERENCE (IPC), 2020,
  • [40] Training Optimization for Gate-Model Quantum Neural Networks
    Gyongyosi, Laszlo
    Imre, Sandor
    SCIENTIFIC REPORTS, 2019, 9 (1)