Architectural and Micro-architectural Techniques for Software Controlled Microprocessor Soft-error Mitigation

A MIPS 4Kc compliant embedded microprocessor core design that incorporates architectural features for software controlled radiation upset recovery is presented. The design uses fault tolerance techniques, i.e., error detection and instruction restart, implemented at the micro-architectural level, with architectural level changes, i.e., new instructions, for error recovery. Fine-grained, self-correcting triple mode redundant circuits protect key architectural state, in addition to dual mode redundancy in the instruction execution pipelines, cache subsystems, and error detection and correction in the register file. The design is implemented in a commercial low standby power 90-nm bulk low standby power CMOS process and the prototype operates at up to 336 MHz.