A "Design for verification" methodology

被引：0
|
作者：
Sforza, F [1 ]
Battù, L [1 ]
Brunelli, M [1 ]
Castelnuovo, A [1 ]
Magnaghi, M [1 ]
机构：
[1] STMicroelectronics, CR&D, NVM Design Platform, I-20041 Agrate Brianza, MI, Italy
来源：
INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2001年
关键词：
functional verification; testbenches; simulation; emulation; prototyping; IP re-use;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
New tools are getting available on the marker that help alleviating the problem and improve the quality of functional verification of today's complex systems. A methodology that makes use of such tools is described and compared to the traditional approach follow ed in the context of a specific project. The scope is limited to functional verification bur spans from block- to system-level.
引用
收藏
页码：50 / 55
页数：6
相关论文
共 50 条
  • [1] A TLM design for verification methodology
    Bombieri, Nicola
    Fummi, Franco
    Pravadelli, Graziano
    [J]. PRIME 2006: 2ND CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONIC AND ELECTRONICS, PROCEEDINGS, 2006, : 337 - +
  • [2] Theory and verification of operator design methodology
    HU ZiYi1
    2Institute of Microelectronics
    [J]. Science China(Information Sciences), 2012, 55 (02) : 480 - 490
  • [3] Commercial design verification: Methodology and tools
    Pixley, C
    Strader, NR
    Bruce, WC
    Park, JH
    Kaufmann, M
    Shultz, K
    Burns, M
    Kumar, J
    Yuan, J
    Nguyen, J
    [J]. INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 839 - 848
  • [4] Theory and verification of operator design methodology
    Hu ZiYi
    Zhao Yong
    Wang XinAn
    Huang Ru
    Wang Teng
    Zhang Xing
    [J]. SCIENCE CHINA-INFORMATION SCIENCES, 2012, 55 (02) : 480 - 490
  • [5] Theory and verification of operator design methodology
    ZiYi Hu
    Yong Zhao
    XinAn Wang
    Ru Huang
    Teng Wang
    Xing Zhang
    [J]. Science China Information Sciences, 2012, 55 : 480 - 490
  • [6] Study on micro controller design and verification methodology
    Kim, KS
    Park, JS
    [J]. KORUS 2003: 7TH KOREA-RUSSIA INTERNATIONAL SYMPOSIUM ON SCIENCE AND TECHNOLOGY, VOL 2, PROCEEDINGS: ELECTRICAL ENGINEERING AND INFORMATION TECHNOLOGY, 2003, : 228 - 233
  • [7] A Design and Verification Methodology for Secure Isolated Regions
    Sinha, Rohit
    Costa, Manuel
    Lal, Akash
    Lopes, Nuno P.
    Rajamani, Sriram
    Seshia, Sanjit A.
    Vaswani, Kapil
    [J]. ACM SIGPLAN NOTICES, 2016, 51 (06) : 665 - 681
  • [8] Promising complex ASIC design verification methodology
    Assaf, Mansour H.
    Das, Sunil R.
    Hermas, Wael
    Jone, Wen-B.
    [J]. 2007 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-5, 2007, : 857 - +
  • [9] An Automatic SoC Design Methodology for Integration and Verification
    Ma, De
    Huang, Kai
    Xiu, SiWen
    Yan, Xiaolang
    Feng, Jiong
    Zeng, JianLin
    Ge, Haitong
    [J]. MANUFACTURING SCIENCE AND TECHNOLOGY, PTS 1-8, 2012, 383-390 : 2222 - 2230
  • [10] DESIGN, VERIFICATION, AND TEST METHODOLOGY FOR A VLSI CHIP SET
    KOHLHARDT, C
    GADDIS, TW
    HALPERIN, DL
    UNDY, SR
    SCHUCHARD, RA
    [J]. HEWLETT-PACKARD JOURNAL, 1987, 38 (09): : 18 - &
12345