A 6.25 mW,+21 dBm OIP3, 0.85 dB NF, 2.5 GHz LNA Employing High Self Gain Device in 0.13 μm SOI Technology

被引:0
|
作者
Vanukuru, Venkata [1 ]
Dutta, Anupam [1 ]
Swaminathan, Balaji [1 ]
Choppalli, Satyasuresh [1 ]
Wolf, Randy [2 ]
Jaffe, Mark [2 ]
Tan, Yue [2 ]
Logan, Ron [2 ]
Monaghan, John Ellis [2 ]
Joseph, Alvin [2 ]
机构
[1] GLOBALFOUNDRIES, RF Design Enablement, Bangalore, Karnataka, India
[2] GLOBALFOUNDRIES, RF Technol Dev, Essex Jct, VT USA
关键词
CMOS technology; low noise amplifier; silicon-on-insulator; MULTIPLE GATED TRANSISTORS; LOW-NOISE AMPLIFIER; CMOS LNA;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, significant improvement in cascode LNA performance is demonstrated by using a new high self gain (HSG) common gate (CG) transistor. Emphasis has been on making the output conductance g(ds) lower and flatter with drain bias. A prototype cascode LNA is designed and fabricated using the developed HSG device in state-of-the-art 0.13 RF SOI technology. Thanks to the HSG device, more than +5 dBm input inter-modulation product (IIP3) improvement is seen in measurements. Very high gain of 19.5 dB at 2.5 GHz with IIP3 value of +1.5 dBm are seen in measurements. Due to optimized transistor sizing, the designed LNA operates at low power of 6.25 mW where 5.2 mA of current is drawn from 1.2 V supply. With integrated high quality factor inductors on high resistivity SOI substrate, the LNA also demonstrates very low noise figure of 0.85 dB. Furthermore, excellent correlation between model simulations and measurements is demonstrated.
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页码:1 / 4
页数:4
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