共 50 条
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- [22] Test Architecture for Fine Grained Capture Power Reduction 2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2019, : 558 - 561
- [24] Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power 2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 371 - 374
- [25] Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing 2020 IEEE 38TH VLSI TEST SYMPOSIUM (VTS 2020), 2020,
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- [29] At-Speed Capture Global Noise Reduction & Low-Power Memory Test Architecture 2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS), 2017,