A Low Capture Power Test Generation Method Using Capture Safe Test Vectors

被引:0
|
作者
Hirai, Atsushi [1 ]
Hosokawa, Toshinori [2 ]
Yamauchi, Yukari [2 ]
Arai, Masayuki [2 ]
机构
[1] Nihon Univ, Grad Sch Ind Technol, Chiba, Japan
[2] Nihon Univ, Coll Ind Technol, Chiba, Japan
关键词
low power; test generation; capture-safe test vectors; test vector synthesis; unsafe faults;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared with the conventional low capture power test generation method.
引用
收藏
页数:2
相关论文
共 50 条
  • [21] Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
    Srivastava, Ankush
    Abraham, Jais
    2022 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2022, : 446 - 455
  • [22] Test Architecture for Fine Grained Capture Power Reduction
    Sun, Yi
    Jiang, Hui
    Ramakrishnan, Lakshmi
    Segal, Matan
    Nepal, Kundan
    Dworak, Jennifer
    Manikas, Theodore
    Bahar, R. Iris
    2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2019, : 558 - 561
  • [23] Efficient Test Set Modification for Capture Power Reduction
    Wen, Xiaoqing
    Suzuki, Tatsuya
    Kajihara, Seiji
    Miyase, Kohei
    Minamoto, Yoshihiro
    Wang, Laung-Terng
    Saluja, Kewal K.
    JOURNAL OF LOW POWER ELECTRONICS, 2005, 1 (03) : 319 - 330
  • [24] Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power
    You, Zhiqiang
    Huang, Jiedi
    Inoue, Michiko
    Kuang, Jishun
    Fujiwara, Hideo
    2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 371 - 374
  • [25] Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing
    Xiang, Dong
    Cai, Jiaming
    Liu, Bo
    2020 IEEE 38TH VLSI TEST SYMPOSIUM (VTS 2020), 2020,
  • [26] Capture-power-aware test data compression using selective encoding
    Li, Jia
    Liu, Xiao
    Zhang, Yubin
    Hu, Yu
    Li, Xiaowei
    Xu, Qiang
    INTEGRATION-THE VLSI JOURNAL, 2011, 44 (03) : 205 - 216
  • [27] Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing
    Li, Yi-Hua
    Lien, Wei-Cheng
    Lin, Ing-Chao
    Lee, Kuen-Jong
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (01) : 127 - 138
  • [28] Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
    Higami, Yoshinobu
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Saluja, Kewal K.
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2013, E96D (06): : 1323 - 1331
  • [29] At-Speed Capture Global Noise Reduction & Low-Power Memory Test Architecture
    Bhaskaran, Bonita
    Chadalavada, Sailendra
    Sarangi, Shantanu
    Valentine, Nithin
    Nerallapally, Venkat Abilash Reddy
    Abdollahian, Ayub
    2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS), 2017,
  • [30] Achieving low capture and shift power in linear decompressor-based test compression environment
    Wang, Weizheng
    Kuang, Jishun
    You, Zhiqiang
    MICROELECTRONICS JOURNAL, 2012, 43 (02) : 134 - 140