A Low Capture Power Test Generation Method Using Capture Safe Test Vectors

被引:0
|
作者
Hirai, Atsushi [1 ]
Hosokawa, Toshinori [2 ]
Yamauchi, Yukari [2 ]
Arai, Masayuki [2 ]
机构
[1] Nihon Univ, Grad Sch Ind Technol, Chiba, Japan
[2] Nihon Univ, Coll Ind Technol, Chiba, Japan
关键词
low power; test generation; capture-safe test vectors; test vector synthesis; unsafe faults;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared with the conventional low capture power test generation method.
引用
收藏
页数:2
相关论文
共 50 条
  • [1] A Dynamic Test Compaction Method on Low Power Test Generation Based on Capture Safe Test Vectors
    Hosokawa, Toshinori
    Hirai, Atsushi
    Yamazaki, Hiroshi
    Arai, Masayuki
    2017 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2017, : 165 - 170
  • [2] A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation
    Hosokawa, Toshinori
    Hirai, Atsushi
    Yamauchi, Yukari
    Arai, Masayuki
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2017, E100D (09): : 2118 - 2125
  • [3] A new method for low-capture-power test generation for scan testing
    Wen, Xiaoqing
    Yamashita, Yoshiyuki
    Kajihara, Seiji
    Wang, Laung-Terng
    Saluja, Kewal K.
    Kinoshita, Kozo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, E89D (05): : 1679 - 1686
  • [4] On low-capture-power test generation for scan testing
    Wen, XQ
    Yamashita, Y
    Kajihara, S
    Wang, LT
    Saluja, KK
    Kinoshita, K
    23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 265 - 270
  • [5] On Generation of Delay Test with Capture Power Safety
    Gulve, Rohini
    Hage, Nihar
    VLSI DESIGN AND TEST, 2017, 711 : 607 - 618
  • [6] Capture Power Reduction Using Clock Gating Aware Test Generation
    Chakravadhanula, Krishna
    Chickermane, Vivek
    Keller, Brion
    Gallagher, Patrick
    Narang, Prashant
    ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 101 - 109
  • [7] Low capture power test generation for launch-off-capture transition test based on don't-care filling
    Wang, Sying-Jyan
    Chen, Yan-Ting
    Li, Katherine Shu-Min
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3683 - +
  • [8] Low-capture-power test generation by specifying a minimum set of controlling inputs
    Lai, Nan-Cheng
    Wang, Sying-Jyan
    PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 413 - 418
  • [9] Reordering and Test Pattern Generation for Reducing Launch and Capture Power
    Stanis, Jonisha S.
    Antony, Maria S.
    2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [10] A Study of Capture-Safe Test Generation Flow for At-Speed Testing
    Miyase, Kohei
    Wen, Xiaoqing
    Kajihara, Seiji
    Yamato, Yuta
    Takashima, Atsushi
    Furukawa, Hiroshi
    Noda, Kenji
    Ito, Hideaki
    Hatayama, Kazumi
    Aikyo, Takashi
    Saluja, Kewal K.
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2010, E93A (07) : 1309 - 1318