VHDL based FPGA implementation of 256-ary PPM for free space optical links

被引：2
|
作者：
Muhammad, S. Sheikh [1 ]
Brandl, P. [1 ]
Leitgeb, E. [1 ]
Koudelka, O. [2 ]
Jelovcan, I. [3 ]
机构：
[1] Graz Univ Technol, Inst Broadband Commun, Infeldgasse 12, A-8010 Graz, Austria
[2] Graz Univ Technol, Inst Satellite Commun & Commun Networks, Infeldgasse 12, A-8010 Graz, Austria
[3] JozefStefan Inst, Dept Commun & Syst, Ljubjlana, Slovenia
来源：
ICTON 2007: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON TRANSPARENT OPTICAL NETWORKS, VOL 3 | 2007年
关键词：
free space optics (FSO); M-ary PPM; FPGA implementation;
D O I：
10.1109/ICTON.2007.4296273
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As the interest in the deployment of Free Space Optical (FSO) links gains momentum, its becoming important to investigate the implementation of proposed higher state modulation schemes. M-ary PPM promises significant performance enhancement and this paper gives results about an experimental VHDL based FPGA implementation of a 256-ary PPM modem. The discussed chip design proves the capability of Wary PPM as an implementable solution for future FSO systems. This preliminary design provides a suitable starting point for an integrated solution in the next generation FSO systems.
引用
收藏
页码：174 / +
页数：2
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