An Ultra-Low-Supply Output-Capacitorless LDO with Signal- and Transient-Enhancement

An ultra-low-supply output-capacitorless (OCL) low-dropout regulator is presented in this paper. The circuit is based on flipped-voltage-follower-based (FVF-based) LDO with a signal-current enhancer (SCE) and a direct voltage-spike detection part. To enable the LDO to function properly under an ultra-low supply voltage, an additional charge-pump circuit provides a higher supply to the control part of LDO to enlarge the control swing of power transistor. The proposed LDO regulator is designed in UMC 65-nm CMOS process. The threshold voltages of NMOSFET and PMOSFET are 0.374 V and -0.311 V, respectively. The achieved minimum supply voltage is 0.6 V, with output voltage of 0.5 V. The load current ranges between 100 mu A and 50 mA. The figure-of-merit of proposed circuit is 0.43 ps.