CHO: Towards a Benchmark Suite for OpenCL FPGA Accelerators

被引：4

作者：

Ndu, Geoffrey ^{[1
]}

Navaridas, Javier ^{[1
]}

Lujan, Mikel ^{[1
]}

机构：

[1] Univ Manchester, Sch Comp Sci, Oxford Rd, Manchester M13 9PL, Lancs, England

来源：

INTERNATIONAL WORKSHOP ON OPENCL 2015 | 2015年

关键词：

OpenCL; FPGA; High Level Synthesis; Accelerator;

D O I：

10.1145/2791321.2791331

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Programming FPGAs with OpenCL-based high-level synthesis frameworks is gaining attention with a number of commercial and research frameworks announced. However, there are no benchmarks for evaluating these frameworks. To this end, we present CHO benchmark suite an extension of CHStone, a commonly used C-based high-level synthesis benchmark suite, for OpenCL. We characterise CHO at various levels and use it to investigate compiling non-trivial software to FPGAs. CHO is work in progress and more benchmarks will be added with time.

引用

页数：10

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