A Processor Accelerator for Software Decoding of BCH Codes

被引：2

作者：

Ito, Kazuhito ^{[1
]}

机构：

[1] Saitama Univ, Grad Sch Sci & Engn, Saitama 3388570, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2010年 / E93A卷 / 07期

关键词：

error correction code; BCH; accelerator; pipelining; COMMUNICATION;

D O I：

10.1587/transfun.E93.A.1329

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.

引用

页码：1329 / 1337

页数：9

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