A new approach for design and verification of transaction level models

被引：4

作者：

Kakoee, Mohammad Reza ^{[1
]}

Shojaei, Hamid ^{[1
]}

Ghasemzadeh, Hassan ^{[1
]}

Sirjani, Marjan ^{[1
]}

Navabl, Zainalabedin ^{[1
]}

机构：

[1] Univ Tehran, Tehran 14399, Iran

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.378779

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product In this paper, we present an approach for design and verification of transaction level models. Verification is integrated as part of the design-flow. In the proposed method, we first model the design in UML. Then, we translate it into the Reactive Objects Language, Rebeca [5], which is an actor-based language with formal foundation. A model in Rebeca is a set of concurrently executed reactive objects (called rebecs) interacted by asynchronous message passing. After mapping UML to Rebeca, Rebeca code will be translated into Promela which is a language for formal verification. Checking the correctness of the design is performed on-the-fly with the LTL properties using the SPIN model checker. Finally, we translate the verified design to SystemC and map the properties to a set of assertions that can be re-used to validate the design at lower levels through simulation.

引用

页码：3760 / 3763

页数：4

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