System-on-Chip Processor using Different FPGA Architectures in the VTR CAD Flow

被引：0
|
作者：
Li, Jingjing [1 ]
Nasartschuk, Konstantin [1 ]
Kent, Kenneth B. [1 ]
机构：
[1] Univ New Brunswick, Fac Comp Sci, Fredericton, NB, Canada
来源：
PROCEEDINGS OF THE 2014 25TH IEEE INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP): SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE | 2014年
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D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Field Programmable Gate Arrays (FPGA) are often the go to choice for system prototyping and comparison. Circuit design and the impact of hardware architecture can be measured and experimented with using short iteration times. The Verilog To Routing (VTR) CAD flow offers a framework for synthesis and experimentation with customizable FPGA architectures. This paper describes the implemented ability to use the VTR flow for tests and experiments with an ARM processor. This includes different possible FPGA architectures for supporting the ARM processor. A thorough set of experiments is performed which aims to determine the impact of hard block memories, multipliers and adders. The results suggest that 2 bit adder units and 36*36 multipliers offer a good choice of parameters.
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收藏
页码：72 / 77
页数：6
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