Novel STI scheme and layout design to suppress the kink effect in LDMOS transistors

被引：5

作者：

Wang, Lei ^{[1
,2
,3
]}

Wang, Jun ^{[1
,2
,3
]}

Li, Rui ^{[1
,2
,3
]}

Lee, Poo ^{[3
]}

Hu, Jian ^{[3
]}

Qu, Will ^{[3
]}

Li, Wenjun ^{[3
]}

Yang, Steve ^{[3
]}

机构：

[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Shanghai, Peoples R China

[2] Chinese Acad Sci, Grad Sch, Beijing, Peoples R China

[3] Grace Semicond Mfg Corp, Shanghai, Peoples R China

来源：

SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2008年 / 23卷 / 07期

关键词：

D O I：

10.1088/0268-1242/23/7/075025

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two simple methods to suppress anomalous subthreshold conduction, the so-called 'kink effect' of lateral double-diffused MOS (LDMOS), were demonstrated. According to TSUPREM-4 simulation and calculation results, LDMOSFETs were more prone to subthreshold kinks than standard CMOSFETs because of the oxidation-enhanced-diffusion (OED) effect and small gate capacitor. The fringing electrical field, which arises from a shallow trench isolation (STI) divot, was remarkably eliminated by the improved isolation scheme. A novel device layout was designed so that the channel dopant segregation can be automatically compensated without any extra processing steps.

引用

页数：5

共 28 条

[1] A NOVEL GATE ARCHITECTURE DESIGN IN STI BASED LDMOS
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[6] Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process
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[7] Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors
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[9] Controlled Kink Effect in a Novel High-Voltage LDMOS Transistor by Creating Local Minimum in Energy Band Diagram
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