Band-to-Band Tunneling Based Ultra-Energy-Efficient Silicon Neuron

被引:33
|
作者
Chavan, Tanmay [1 ]
Dutta, Sangya [1 ]
Mohapatra, Nihar R. [2 ]
Ganguly, Udayan [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Mumbai 400076, Maharashtra, India
[2] IIT Gandhinagar, Dept Elect Engn, Gandhinagar 382355, Gujarat, India
关键词
Band-to-band tunneling (BTBT); leaky integrate-and-fire (LIF); neuron; silicon-on-insulator (SOI); SPIKING NEURONS; INTEGRATE;
D O I
10.1109/TED.2020.2985167
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The human brain comprises about a hundred billion neurons connected through quadrillion synapses. Spiking neural networks (SNNs) take inspiration from the brain to model complex cognitive and learning tasks. Neuromorphic engineering implements SNNs in hardware, aspiring to mimic the brain at scale (i.e., 100 billion neurons) with biological area and energy efficiency. The design of ultra-energy-efficient and compact neurons is essential for the large-scale implementation of SNNs in hardware. In this article, we have experimentally demonstrated a partially depleted (PD) silicon-on-insulator (SOI) MOSFET-based leaky integrate-and-fire (LIF) neuron, where energy efficiency and area efficiency are enabled by two elements of the design-first is the tunneling-based operation and the second is a compact subthreshold SOI control circuit design. Band-to-band tunneling (BTBT)-induced hole storage in the body is used for the "integrate" function of the neuron. A compact control circuit "fires" a spike when the body's potential exceeds the firing threshold. The neuron then "resets" by removing the stored holes from the body contact of the device. Additionally, the control circuit provides "leakiness" in the neuron, which is an essential property of the biological neurons. The proposed neuron provides 10 x higher area efficiency compared to the CMOS design with equivalent energy/spike. Alternatively, it has a 10(4) x higher energy efficiency at area-equivalent neuron technologies. Biologically comparable energy efficiency and area efficiency, along with CMOS compatibility, make the proposed device attractive for large-scale hardware implementation of SNNs.
引用
收藏
页码:2614 / 2620
页数:7
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