Mapping multirate multidimensional Digital Signal Processing systems to efficient computer architectural models by multidimensional unfolding

A direct mapping of multirate Digital Signal Processing (DSP) algorithms to hardware would require data to move at different rates in circuits on the chip, which involves low hardware utilization, complicate routing and synchronization of multiple clock signals. This paper contributes to mapping multidimensional multirate DSP algorithms to uniform-rate special-purpose efficient computer architectural models. Based on the analysis of the reduction of the translated MultiRate Multidimensional Data Flow Graphs, we map multirate multidimensional DSP algorithms to practical architectural models with an extended Push-Up scheduling method.