Hardware Design of Cryptographic Accelerator

被引：0

作者：

Hulic, Michal ^{[1
]}

Vokorokos, Liberios ^{[1
]}

Adam, Norbert ^{[1
]}

Fecil'ak, Peter ^{[1
]}

机构：

[1] Tech Univ Kosice, Fac Elect Engn & Informat, Dept Comp & Informat, Letna 9, Kosice 04200, Slovakia

来源：

2018 IEEE 16TH WORLD SYMPOSIUM ON APPLIED MACHINE INTELLIGENCE AND INFORMATICS (SAMI 2018): DEDICATED TO THE MEMORY OF PIONEER OF ROBOTICS ANTAL (TONY) K. BEJCZY | 2018年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The goal of this paper is representation of computing unit focused on implementation hardware cryptography accelerator. After analysis of assigned problem, there are next chapters dedicated to available solutions, comparison of them, the issues of cryptography and computer security, FPGA device in which the designed solution is verified and tested, the chapters dedicated to cryptography algorithm RSA. Chapters of synthesis have the specifically implemented and designed solution in programming languages of lower and higher level. In evaluation and conclusion chapter there are measurements on software and hardware level and comparison among them.

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页码：201 / 206

页数：6

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