Design and Implementation of Synchronization Detection for IEEE 802.15.3c

被引：0

作者：

Huang, Ya-Shiue ^{[1
]}

Liu, Wei-Chang ^{[1
]}

Jou, Shyh-Jye ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

来源：

2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2011年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).

引用

页码：83 / 86

页数：4

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