Warpage and Thermal Characterization of Fan-out Wafer-Level Packaging

被引：19

作者：

Lau, John ^{[6
]}

Li, Ming ^{[6
]}

Tian, DeWen ^{[6
]}

Fan, Nelson ^{[6
]}

Kuah, Eric ^{[6
]}

Kai, Wu ^{[6
]}

Li, Margie ^{[6
]}

Hao, JiYuen ^{[6
]}

Cheung, Ken ^{[6
]}

Li, Zhang ^{[5
]}

Tan, Kim Hwee ^{[5
]}

Beica, Rozalia ^{[4
]}

Ko, Cheng-Ta ^{[3
]}

Chen, Yu-Hua ^{[3
]}

Lim, Sze Pei ^{[2
]}

Lee, Ning Cheng ^{[2
]}

Wee, Koh Sau ^{[1
]}

Ran, Jiang ^{[1
]}

Xi, Cao ^{[1
]}

机构：

[1] Huawei Technol Co Ltd, Shenzhen, Peoples R China

[2] Indium Corp, Clinton, NY USA

[3] Unimicron Technol Corp, Taoyuan, Taiwan

[4] Dow Chem Co USA, Midland, MI 48674 USA

[5] Jiangyin Changdian Adv Packaging Co Ltd, Jiangyin, Peoples R China

[6] ASM Pacific Technol Ltd, Almere, Netherlands

来源：

2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017) | 2017年

关键词：

D O I：

10.1109/ECTC.2017.309

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this study, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, carrier material and thickness, and die-attach film, on the warpage after post mold cure (PMC) and backgrinding of the EMC. The simulation results are compared with the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

引用

页码：595 / 602

页数：8

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