HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realising numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilising the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates (2,3,4). In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilised to develop optical router and filter products for fibre optics telecommunications and high precision accelerometers. SOI MEMS allows thicker structures, common with bulk micromachining, to be integrated with CMOS, as utilised in surface micromachining. The buried sacrificial oxide layer enables 3-D structures to be implemented in single crystal silicon which removes the stress associated with polysilicon. This offers substantial improvements in increased lateral sensitivity for inertia applications and it facilitates the removal of the perforated surface in MOEMS designs by etching through the handle wafer to release the mirrors. Although the Bosch process was the catalyst that allowed High Aspect Ratio Micromachining (HARM) products to be developed, processes have historically been restricted to bulk micromachining due to the lateral etch characteristics, at the buried oxide interface, for SOI substrates. Several SOI etch processes will be presented that clearly demonstrate the elimination of this notching effect. These applications will include multi feature SOI etching to oxide and through the wafer anisotropic etching.