Design and Implementation of TLS Accelerator

被引:1
|
作者
Yildiz, Recep Onur [1 ]
Yilmazer-Metin, Ayse [1 ]
机构
[1] Istanbul Tech Univ, Comp Engn Dept, Istanbul, Turkey
来源
PROCEEDINGS OF THE 2022 15TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS 2022) | 2022年
关键词
TLS; accelerator; FPGA;
D O I
10.1109/DCAS53974.2022.9845527
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Communication devices deploy messages to another one over either a controlled channel or a non-controlled channel. When the communication channel is non-controlled, the deployed message is available for anyone that is able to listen. But, the deployed message may comprise private information that needs to be shared securely. Therefore, to establish a secure communication over a controlled or a non-controlled channel, cryptography algorithms are used. The Transport Layer Security (TLS) is a protocol that includes several cryptography algorithms. With its algorithms, TLS provides authentication, confidentiality, and data integrity features. These features achieved with repeated calculations. Yet, these calculations increase the power consumption and degrade the performance of a sequential processor. To overcome these problems, an accelerator can be used for the calculations of TLS protocol. In this work, a TLS accelerator is designed and implemented on an FPGA. Our design aims to increase the performance and decrease the power consumption of sequential processor during the TLS calculations. The proposed accelerator is implemented with Xilinx Vivado and the implementation results show that the proposed accelerator consumes 0.86 Watt power. The accelerator is simulated with Vivado in order to measure the throughput of the proposed accelerator. The encryption throughput of the proposed accelerator at 100 MHz operating frequency is observed as 700 Mbps. Also, the proposed accelerator provides 52.4 handshake connections per second.
引用
收藏
页数:4
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