Design of an Improved Successive Approximation Type ADC using Multi bit per Cycle Algorithm for Conversion Rate Improvement

The paper presents an improved analog-to-digital converter (ADC) architecture based upon traditional successive approximation register (SAR) type ADC concepts. The most important aspect of the present design is that it resolves two or more bits in a single cycle and hence requires much lesser time than a conventional SAR ADC for conversion of same resolution. A 12-bit, 3-bit per cycle ADC logic was simulated in MATLAB SIMULINK for verification of the design. The design requires only 4 clock cycles to accomplish the conversion unlike its conventional counterpart which would require thirteen clock cycles. Seven comparators are used in parallel to resolve 3 bits during each conversion cycle. Divide and conquer algorithm is utilized here instead of the regular binary search algorithm employed for conventional SAR ADCs. Emphasis is placed on latency minimization at the cost of a nominal increase in component cost, i.e., space requirement for a particular semiconductor technology. Simulation results establish the validity of the proposed method.