Design and verification driven by assertions

被引：0
|
作者：
Torres, F [1 ]
Vaca, S [1 ]
Torres, D [1 ]
González, RE [1 ]
机构：
[1] IPN, CINVESTAV, Unidad Guadalajara, Zapopan 45090, Jalisco, Mexico
来源：
2004 1st International Conference on Electrical and Electronics Engineering (ICEEE) | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper we propose an improvement of the design cycle of synchronous circuits. The use of semi-formal specifications was necessary to write good code and to perform a formal verification using a model checking tool. Our first results show that the implemented code has several advantages with respect to others written with classical methodologies, and we rind that formal and functional verification are complementary.
引用
收藏
页码：188 / 193
页数：6
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