Hot-carrier-induced degradation under current saturation bias in p-channel low-temperature polycrystalline silicon thin-film transistors

A two-dimensional (2-D) physical model of p-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) was proposed to analyze hot-carrier degradation based on a 2-D device and process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate. It can be predicted from the 2-D device simulation and experimental results that hot-electron trapping at both upper and bottom interfaces can contribute to hot-carrier degradation under current saturation stress. The degradation will first occur in a high-field region in the p(+) drain region, and, with the increase in stress time, the electron-trapped region expands mainly toward the channel. For high-vertical bar V-d vertical bar bias, a decrease in impact ionization due to the presence of the trapped charges will reduce the drain current, resulting in the reduction in kink current. In low-vertical bar V-d vertical bar bias, the current flow after the long-time stress is located at the upper and bottom interfaces near the drain junction due to trapped electrons and the trapped charges at both interfaces will result in the enhancement of the V-g-I-d characteristics.