Anomalous hot-carrier-induced degradation of offset gated polycrystalline silicon thin-film transistors

Hot-carrier effects in offset gated n-channel polycrystalline silicon thin-film transistors of channel length L = 10 mum and intrinsic offset lengths DeltaL = 0.5 and 1 mum are investigated. The gate- and drain-bias conditions for maximum device degradation were determined from substrate current measurements. The experimental data show that hot-carrier stress provokes an anomalous threshold voltage and on-state current degradation, exhibiting a "staircase-like" degradation with stress time. These results lead to the conclusion that, at the initial stages of stress, a small offset region from the drain end is damaged due to charging of the grain boundaries. As the stress proceeds further and the grain boundary traps are filled with electrons generated by impact ionization, the damage is transferred to the neighboring offset region, resulting in a staircase-like degradation of the device parameters with stress time. (C) 2004 American Institute of Physics.