Framework for mapping scalable networked multimedia applications on run-time reconfigurable platforms

被引:0
|
作者
Ngoc, NP [1 ]
Lafruit, G [1 ]
Mignolet, JY [1 ]
Vernalde, S [1 ]
Deconinck, G [1 ]
Lauwereins, R [1 ]
机构
[1] Katholieke Univ Leuven, ESAT, EELCTA, B-3001 Louvain, Belgium
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Due to the heterogeneous nature of networks and end-systems in distributed multimedia systems, multimedia applications should ideally be designed to counteract fluctuations in network bandwidth and end-system processing capacities for providing end users a certain degree of Quality of Service (QoS). This requirement can be satisfied with scalable applications. In addition, with the current evolution in run-time reconfigurable computing, run-time reconfigurable multimedia platforms are becoming increasingly viable. In this paper, an end-to-end delivery chain framework for mapping scalable networked multimedia applications on reconfigurable platforms is presented. The framework is demonstrated by a case study of a 3D game running on a prototype run-time reconfigurable platform.
引用
收藏
页码:469 / 472
页数:4
相关论文
共 50 条
  • [21] Run-time verification of networked software
    Research Center for Information Security , National Institute of Advanced Industrial Science and Technology , Tokyo, Japan
    [J]. Lect. Notes Comput. Sci., (59-73):
  • [22] Run-time Mapping Algorithm for Dynamic Workloads on Heterogeneous MPSoCs Platforms
    Sinaei, Sima
    Fatemi, Omid
    [J]. 2018 21ST EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2018), 2018, : 373 - 380
  • [23] A Run-time Reconfigurable Cache Architecture
    Nowak, Fabian
    Buchty, Rainer
    Karl, Wolfgang
    [J]. PARALLEL COMPUTING: ARCHITECTURES, ALGORITHMS AND APPLICATIONS, 2008, 15 : 757 - +
  • [24] Run-time reconfigurable systems for digital signal processing applications: A survey
    Shoa, A
    Shirani, S
    [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2005, 39 (03): : 213 - 235
  • [25] Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
    Alireza Shoa
    Shahram Shirani
    [J]. Journal of VLSI signal processing systems for signal, image and video technology, 2005, 39 : 213 - 235
  • [26] Run-Time Partially Reconfigurable FPGA Applications in PV Fed Systems
    Kumar, Sajeesh
    Agarwal, Vivek
    [J]. IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES 2012), 2012,
  • [27] Context switching in a run-time reconfigurable system
    Puttegowda, K
    Lehn, DI
    Park, JH
    Athanas, P
    Jones, M
    [J]. JOURNAL OF SUPERCOMPUTING, 2003, 26 (03): : 239 - 257
  • [28] Run-time requirements verification for reconfigurable systems
    Chatzikonstantinou, George
    Kontogiannis, Kostas
    [J]. INFORMATION AND SOFTWARE TECHNOLOGY, 2016, 75 : 105 - 121
  • [29] Run-time Task Overlapping on Multiprocessor Platforms
    Ma, Zhe
    Catthoor, Francky
    [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 60 (02): : 169 - 182
  • [30] Modelling and optimising run-time reconfigurable systems
    Luk, W
    Shirazi, N
    Cheung, PYK
    [J]. IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS, 1996, : 167 - 176