Assessment of Thinned Si Wafer Warpage in 3D Stacked Wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. Among many technical challenges in 3D stacked wafers the wafer warpage is one of the important processing issues to be resolved because the wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, WIW (within wafer) non-uniformity and electrical failure. In this study the wafer warpage of thinned Si wafer in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate and Cu or polyimide was used as a bonding material with Si wafer. The top Si wafer on bonded stacks was ground down to 20 similar to 100 mu m and wafer curvature was measured. Wafer curvature depending upon bonding material, substrate material, CTE (coefficient of thermal expansion) of stacked layers, and thickness of thinned Si wafer will be discussed.