Architecture driven partitioning

被引:0
|
作者
Küter, J [1 ]
Barke, E [1 ]
机构
[1] Infineon Technol AG, MP TI CS ATS, D-81541 Munich, Germany
关键词
D O I
10.1109/DATE.2001.915067
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper. M e present a new algorithm to partition netlists for logic emulation under consideration of the targeted emulator architecture. The proposed algorithm allows the flexible use for a wide variety of applications because the description of the archirecture is parr of the input data. It combines a new approach of finding and improving an initial solution with existing algorithms to cluster the netlist and optimize the number of cut nets between blocks. As a result, the algorithm ensures that the cut nets between the created blocks can be connected within the emulation system, even without a full interconnect structure. Experiments an a number of designs and architectures demonstrate that the algorithm is competitive for architectures with full inrerconnect and that it is unique for architectures with limited interconnect resources.
引用
收藏
页码:479 / 485
页数:7
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