Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing

被引:5
|
作者
Zhou, Zheng [1 ]
Plishker, William [2 ]
Bhattacharyya, Shuvra S. [2 ]
Desnos, Karol [3 ]
Pelcat, Maxime [3 ]
Nezan, Jean-Francois [3 ]
机构
[1] Texas Instruments Inc, Germantown, MD USA
[2] Univ Maryland, Dept ECE & UMIACS, College Pk, MD 20742 USA
[3] UEB, CNRS, INSA Rennes, IETR,UMR 6164, Rennes, France
关键词
Multicore processors; Digital signal processors; Synchronous dataflow; Dataflow modeling; Software synthesis;
D O I
10.1007/s11265-014-0956-2
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous Dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra-and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) - PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a software defined radio benchmark on a state-of-the-art multicore DSP platform.
引用
收藏
页码:309 / 328
页数:20
相关论文
共 50 条
  • [41] OPTIMIZED AND PARALLELIZED PROCESSING ORDER FOR IMPROVED FREQUENCY SELECTIVE SIGNAL EXTRAPOLATION
    Seiler, Juergen
    Kaup, Andre
    19TH EUROPEAN SIGNAL PROCESSING CONFERENCE (EUSIPCO-2011), 2011, : 269 - 273
  • [42] High-Level Synthesis of Dataflow Programs for Signal Processing Systems
    Bezati, Endri
    Mattavelli, Marco
    Janneck, Jorn W.
    2013 8TH INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS (ISPA), 2013, : 750 - +
  • [43] DECIDABLE VARIABLE-RATE DATAFLOW FOR HETEROGENEOUS SIGNAL PROCESSING SYSTEMS
    Ma, Yujunrong
    Wu, Jiahao
    Bhattacharyya, Shuvra S.
    Boutellier, Jani
    2020 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2020, : 1683 - 1687
  • [44] Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators
    Rossi, Davide
    Mucci, Claudio
    Pizzotti, Matteo
    Perugini, Luca
    Canegallo, Roberto
    Guerrieri, Roberto
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (09) : 1990 - 2003
  • [45] Selective Grating Inscription in Multicore Fibers for Radiofrequency Signal Processing
    Gasulla, Ivana
    Barrera, David
    Hervas, Javier
    Sales, Salvador
    2017 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXHIBITION (OFC), 2017,
  • [46] Dataflow Programming of Real-time Radar Signal Processing on Manycores
    Ul-Abdin, Zain
    Yang, Mingkun
    2014 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP), 2014, : 15 - 19
  • [47] Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization
    Liu, Weichen
    Yuan, Mingxuan
    He, Xiuqiang
    Gu, Zonghua
    Liu, Xue
    RTSS: 2008 REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2008, : 492 - +
  • [48] Synchronous SRAM for digital signal processing applications
    Shulman, D
    ELECTRONICS LETTERS, 1997, 33 (07) : 562 - 564
  • [49] Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
    Voigt, S.
    Baesler, M.
    Teufel, T.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 56 (11) : 561 - 576
  • [50] Generating compact code from dataflow specifications of multirate signal processing algorithms
    Bhattacharyya, Shuvra S.
    Buck, Joseph T.
    Ha, Soonhoi
    Lee, Edward A.
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1995, 42 (03): : 138 - 150