CMOS Current-Mode PWL Implementation using MAX and MIN Operators

被引：0

作者：

Cinco-Izquierdo, O. J. ^{[1
]}

Sanz-Pascual, M. T. ^{[1
]}

Hernandez, L. ^{[1
]}

de la Cruz-Blas, C. A. ^{[2
]}

机构：

[1] Inst Nacl Astrofis Opt & Elect INAOE, Elect Dept, Puebla, Mexico

[2] Univ Publ Navarra UPNA, Dept Elect & Elect Engn, Pamplona, Spain

来源：

2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2017年

关键词：

Current-mode; PWL approximation; Winner-Take-All; Loser-Take-All; exponential function; logarithmic function;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this manuscript a novel current-mode technique to implement generic Piecewise-Linear (PWL) functions is presented. The main characteristic of the proposed circuits is that errors are not accumulated by adding linear segments; instead they are local, providing more robust designs. The proposed circuits are designed in a standard 0.18 mu m CMOS process with 1.8V power supply. Their operation is based on high precision current mirrors, Winner-Take-All (WTA) and Loser-Take-All (LTA) architectures. Robustness was verified by Monte Carlo analysis and temperature variations from -40 degrees C to 80 degrees C.

引用

页数：4

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