Balanced scheduling and operation, chaining in high-level synthesis for FPGA designs

被引:0
|
作者
Zaretsky, David C. [1 ]
Mittal, Gaurav [1 ]
Dick, Robert P. [2 ]
Banerjee, Prith [1 ]
机构
[1] Univ Illinois, Dept Elect & Comp Engn, 851 S Morgan St, Chicago, IL 60607 USA
[2] Northwestern Univ, Dept Elect Engn & Comp Sci, Evanston, IL 60208 USA
基金
美国国家科学基金会;
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced scheduling routine that uniformly distributes operations across states to reduce critical timing paths in the absence of accurate functional unit delay models. On average, results show, improvements in frequency, and run times for balanced scheduling over ASAP, ALAP, and force-directed scheduling. Additionally, we provide a methodology for precision-based delay modeling of operations. We present a balanced chaining routine that, given a target frequency, uses this modeling technique to reduce the number of clock cycles in the design. Results show, approximately 20% improvement on average in run times when incorporating our balanced chaining routine with scheduling. Applying balanced chaining in a high-level synthesis tool allowed performance improvements between 8-29x for large, complex applications. Our method for modeling operation delays is shown to be accurate in estimating delays for operation chaining during high-level synthesis.
引用
收藏
页码:595 / +
页数:2
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