A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET

被引：0
|
作者：
Kim, Min-Sik [1 ]
Cho, Kang-Il [1 ]
Kwak, Yong-Sik [1 ]
Lee, Sangwon [1 ]
Choi, Jaewoo [1 ]
Ahn, Gil-Cho [1 ]
机构：
[1] Sogang Univ, Dept Elect Engn, Seoul 121742, South Korea
来源：
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2017年 / 17卷 / 06期
关键词：
Positron emission tomography (PET); time-to-digital converter (TDC); time of flight (TOF); phase-locked loop (PLL); delay-locked loop (DLL); vernier delay line (VDL); anger logic; DELAY-LINE; TDC; PLL;
D O I：
10.5573/JSTS.2017.17.6.800
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a 19.5 ps-LSB vernier-type time-to-digital converter (TDC) to measure the time of flight in a positron emission tomography (PET) imaging system. An 8x8 SiPMs sensor array coupled to LYSO (Lutetium Yttrium Orthosilicate) scintillator crystals are utilized with an anger logic readout circuit to reduce the total number of analog front-end (AFE) channels. The proposed TDC consists of a 5-bit MSB counter and a 6-bit LSB vernier delay line (VDL) TDC that is controlled by an internal delayed-locked loop. A phase-locked loop is integrated for frequency multiplication to increase the time resolution. The prototype chip is fabricated in a 0.18 mu m CMOS technology. The measured timing resolutions of the prototype TDC are 400ps with a 333 kHz external input and 5ns using a Na-22 point gamma-ray source with an 8x8 SiPMs sensor array and anger logic readout circuit. The prototype TDC consumes 180 mW with a 1.8 V supply voltage while occupying a 1.76 mm(2) of the active area.
引用
收藏
页码：800 / 805
页数：6
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