Rectilinear floorplanning of FPGAs using Kohonen map

In this paper, we present an algorithm for the floorplanning of FPGAs (field-programmable gate arrays). The algorithm uses Kohonen self-organizing map to floorplan regular structures with soft modules. An abstract specification of the design is converted to a set of appropriate input vectors, which are fed to the network. At the end of the process, the map shows a two-dimensional plane of the design in which the modules with higher connectivity are placed adjacent to each other, hence minimizing total connection length in the design. Unlike conventional floorplanning algorithms, which are limited to rectangular shapes, our approach can produce rectilinear modules. Using Kohonen map enables the algorithm to do 3-dimensional floorplanning.