Vertically Integrated Circuits: Example of an Application to an x-ray Detector

被引:0
|
作者
Marras, A. [1 ]
Allahgholi, A. [1 ]
Becker, J. [1 ]
Bianco, L. [1 ]
Delfs, A. [1 ]
Goettlicher, P. [1 ]
Klyuev, A. [1 ]
Jack, S. [1 ]
Lange, S. [1 ]
Sheviakov, I. [1 ]
Trunk, U. [1 ]
Xia, Q. [1 ]
Zhang, J. [1 ]
Zimmer, M. [1 ]
Dinapoli, R. [2 ]
Greiffenberg, D. [2 ]
Mezza, D. [2 ]
Mozzanica, A. [2 ]
Schmitt, B. [2 ]
Shi, X. [2 ]
Klanner, R. [3 ]
Schwandt, J. [3 ]
Graafsma, H. [1 ,4 ]
机构
[1] DESY, Photon Sci Detector Grp, Hamburg, Germany
[2] Paul Scherrer Inst, SLS Detector Grp, Villigen, Switzerland
[3] Univ Hamburg, Hamburg, Germany
[4] Mid Sweden Univ, Sundsvall, Sweden
关键词
3DIC; Vertically integrated circuit; AGIPD; x-ray detector; FEL;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Replacing planar circuits with vertically integrated ones allows to increment circuit functionalities on a given silicon area, while avoiding some of the problems associated with aggressively scaled technology nodes. This is particularly true for applications likely to subject circuits to high doses of ionizing radiation (such of x-ray detectors to be used in synchrotron rings and Free Electron Lasers), since the degradation mechanisms of some of the innovative materials to be used in most recent nodes have not been fully characterized yet. In this paper, an evolution is presented for the readout ASIC of a pixelated x-ray detector to be used for such applications. The readout circuit is distributed in a stack of two vertically interconnected tiers, thus doubling the circuitry resident in each pixel without increasing the pixel pitch (and thus compromising spatial resolution of the detector). A first prototype has been designed and manufactured, using a commercial 130nm CMOS technology. Design issues are discussed, along with preliminary characterization results.
引用
收藏
页码:243 / 246
页数:4
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