Block Copolymer Directed Self-Assembly Enables Sublithographic Patterning for Device Fabrication

被引:20
|
作者
Wong, H. -S. Philip [1 ]
Bencher, Chris [2 ]
Yi, He [1 ]
Bao, Xin-Yu [1 ]
Chang, Li-Wen [1 ]
机构
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[2] Appl Mat Inc, Santa Clara, CA 95054 USA
来源
关键词
D O I
10.1117/12.918312
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
The use of block copolymer self-assembly for device fabrication in the semiconductor industry has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey [1-2] have shown a high degree of dimensional control of the self-assembled features over large areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. The need to coax the self-assembled features into circuit layout friendly location is a roadblock for introducing self-assembly into semiconductor manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly (graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm contact holes for practical circuits. Recognizing that typical circuit layouts do not require long range order, we adopt a lithography sub-division approach akin to double-patterning and spacer patterning. Guiding topographical templates with sizes of the order of the natural pitch of the block copolymer can effectively guide the placement of block copolymer features at arbitrary locations irrespective of the natural (often hexagonal for cylindrical domains) arrangements of the block copolymer [5] (Fig. 1). This is possible because the forces from the lateral confinement from sidewall of the small topographical template are strong. Using small topographical templates, contact hole patterns that are often used in circuit layouts can be placed at arbitrary location by first patterning a coarse guiding template using conventional lithography [5-6] (Fig. 2). This procedure is akin to double-patterning and spacer patterning where a coarse lithographic pattern is used to generate a higher resolution feature at a location determined by the coarse lithographic pattern. The size and registration of the features are determined by parameters of the template as well as the block copolymer itself. Preliminary analysis of the size and positional accuracy of small template DSA shows great promise [6] (Fig. 3). To illustrate the use of this small template DSA approach, we use 193 nm immersion lithography to print the templates for 22-nm node SRAM cells reported by IBM [7]. The contact for the polysilicon-to-diffusion cross-over of the SRAM cell is implemented by a two-hole contact pattern (Fig. 2c) instead of an elliptical contact in the original design (Fig. 4). Well-formed contact hole patterns with good positional accuracy are obtained (Fig. 5) using only one lithography step followed by block copolymer DSA. Pattern transfer of the block copolymer soft mask into device layers is necessary for device fabrication. Using conventional reactive ion etching, DSA contact hole patterns are transferred to dielectric layers and subsequently filled with metals that make electrical contact to the devices [8] (Fig. 6). Transistors and simple circuits such as inverters have been demonstrated using block copolymer DSA for contact hole patterning [8] (Fig. 7). The contact holes for more complex random logic circuits patterned by this small template DSA approach has also been demonstrated for selected standard cells in an open-source standard cell library adapted for 22-nm node CMOS [9]. One of the main concerns for the commercialization of directed self-assembly (DSA) for semiconductor manufacturing is defectivity. A common application for this small template approach is to form a single hole for each coarse template (Fig. 2a) (hole-in-hole). The missing via defectivity rate using this DSA hole-shrink technique has recently been reported by others to be less than 1-per-25-million vias [10]. This result reinforces the commercializability of this patterning technique.
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页数:7
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