High speed sample and hold design using closed-loop pole-zero cancelation

A new closed loop Sample-and-Hold (S&H) architecture is proposed for pipeline analog-to-digital converter (ADC) that breaks the precision-speed-power trade off by means of canceling out the first closed loop pole. This pole-canceling results in widening the bandwidth of the S&H up to the second pole. In this architecture, two amplifiers are used: one for accuracy with little power consumption, another one for high-speed response, which consumes most of the total power. Exploiting these two amplifiers remedies some of the tradeoffs and limitations of opamp design in S&H circuits. Simulated by HSPICE with a standard BSIM3v3 0.13 mu m technology, the S&H achieves 80 dB SFDR for a 1.6 V-ppd output at 500 MHz sampling rate. (C) 2011 Elsevier Ltd. All rights reserved.