A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

被引：0

作者：

Song, Yan ^{[1
,2
]}

Zhu, Yan ^{[1
]}

Chan, Chi-Hang ^{[1
]}

Geng, Li ^{[2
]}

Martins, Rui Paulo ^{[1
]}

机构：

[1] Univ Macau, State Key Lab Analog & Mixed Signal VLSI, DECE FST, Macau, Peoples R China

[2] Xi An Jiao Tong Univ, Sch Microelect, Xian, Shaanxi, Peoples R China

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a wide-band and energy-efficient 0-1 MASH Sigma Delta ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2n d -stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.

引用

页码：203 / 204

页数：2

共 16 条

[1] A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC
Song, Yan
Chan, Chi-Hang
Zhu, Yan
Martins, Rui P.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55 (02) : 312 - 321
[2] A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure
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Oh, Younggyun
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Kim, Jintae
Chae, Hyungil
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[3] A 77dB SNDR, 4MHz MASH ΔΣ Modulator with a Second-Stage Multi-rate VCO-Based Quantizer
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[4] An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure
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[5] A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation
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[6] A 12b 330MS/s Pipelined-SAR ADC with PVT-Stabilized Dynamic Amplifier Achieving <1dB SNDR Variation
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2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 472 - 472
[7] A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC
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[8] A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation
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[9] A 1V 56.07dB SNDR 10MHz Bandwidth Digital Slope ADC Based on Preset Bidirectional-Shifting Technique
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[10] A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (02) : 433 - 447

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