Thermal management of lateral GaN power devices

被引：0

作者：

Yu, Chenjiang ^{[1
]}

Laboure, Eric ^{[1
]}

Buttay, Cyril ^{[2
]}

机构：

[1] UPMC, Univ Paris 11, Cent Supelec, Lab GEEPS,UMR 8507, 11 Rue Joliot Curie, FR-91192 Gif Sur Yvette, France

[2] Univ Lyon, CNRS, INSA Lyon, Lab Ampere,UMR 5005, F-69621 Villeurbanne, France

来源：

2015 IEEE INTERNATIONAL WORKSHOP ON INTEGRATED POWER PACKAGING (IWIPP) | 2015年

关键词：

GaN power device; thermal management; Flex circuit; 3D packaging; flip-chip;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article investigates several thermal management techniques for GaN transistors with a Wafer-Level Packaging (WLP): advanced techniques are used to mount them on Direct-Bonded Copper (DBC) ceramic substrates, with the heat removed either through the topside of the die (as recommended by the manufacturer), or through the backside. The thermal resistance of the assembly is measured in the different configurations, for different die thicknesses. The paper describes the manufacturing process and the thermal simulation and experimental results will be shown.

引用

页码：40 / 43

页数：4

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