On the design of scalable massively parallel CRC circuits

被引：2

作者：

Septinus, Konstantin ^{[1
]}

Le, Thuyen ^{[2
]}

Mayet, Ulrich ^{[2
]}

Pirsch, Peter ^{[1
]}

机构：

[1] Inst Microelect Syst, Appelstr 4, D-30167 Hannover, Germany

[2] IBM Deutschland Entwicklung GmbH, D-71032 Boblingen, Germany

来源：

2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4 | 2007年

关键词：

D O I：

10.1109/ICECS.2007.4510950

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a scalable massively parallel CRC architecture for high-speed network processing. The proposed method considers wide data busses, which result in highest throughput. In addition, data streams are processed without interrupts. An investigated 65nm-ASIC implementation example for 32-bit CRC encoding operates on 58 GBps data streams at reasonable costs (0.036 mm(2)). The proposed method can be exploited furthermore in order to develop a configurable circuit for a group of generator polynomials, without the requirement of fully programmable architecture.

引用

页码：142 / +

页数：2

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