On the advantages of serial architectures for low-power reliable computations

This paper explores low-power reliable micro-architectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V-th). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low-power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180nm, 120nm, and 70nm) identify the supply voltages where the power-delay- and energy-delay-products are minimized. These show that redundant serial adders are not only low-power and reliable, but can trade speed for power in a wide range (by varying V-DD both above and below V-th).