ULTRA-LOW-POWER LOW DROP-OUT (LDO) VOLTAGE REGULATOR WITH IMPROVED POWER SUPPLY REJECTION

Having a high-power supply rejection (PSR) over a wide range of frequencies is a very important specification for most of low-dropout voltage regulators (LDOs). A low-power LDO with 2 methods of high-frequency PSR and loop stability compensation techniques is presented in this paper. The proposed LDO achieves a high PSR over a wide frequency range with low power and small area consumption. The LDO is implemented in 65 nm CMOS technology and achieves a PSR better than 77 dB up to 30 MHz for output load currents up to 25 mA and a 4 mu F output load capacitor. The design is suitable for capacitor loaded (Capped) LDOs with a wide output load current range up to 100 mA and output load capacitor range from 1 mu F to 12 mu F. The proposed LDO consumes a no-load quiescent current of 5 mu A and an area of 400 mu m x 200 mu m.