Coverage of formal properties based on a high-level fault model and functional ATPG

被引：8
|
作者：
Fummi, F [1 ]
Pravadelli, G [1 ]
Toto, F [1 ]
机构：
[1] Univ Verona, Dipartimento Informat, I-37100 Verona, Italy
来源：
ETS 2005:10TH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/ETS.2005.12
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The use of model checking to validate descriptions of digital systems lacks a coverage metrics. If the set of formal properties defined to prove the correctness of the design is incomplete, the verification can lead to a false sense of security. This paper refines, extends, and compares with other symbolic approaches, a methodology to estimate the incompleteness of formal properties, which exploits a high-level fault model and functional ATPG.
引用
下载
收藏
页码：162 / 167
页数：6
相关论文
共 50 条
  • [1] High-level observability for effective high-level ATPG
    Corno, Fulvio
    Sonza Reorda, Matteo
    Squillero, Giovanni
    Proceedings of the IEEE VLSI Test Symposium, 2000, : 411 - 416
  • [2] Effective techniques for high-level ATPG
    Corno, F
    Cumani, G
    Reorda, MS
    Squillero, G
    10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 225 - 230
  • [3] On the use of a high-level fault model to check properties incompleteness
    Fummi, F
    Pravadelli, G
    Fedeli, A
    Rossi, U
    Toto, F
    FIRST ACM AND IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2003, : 145 - 152
  • [4] Formal methods for analyzing the completeness of an assertion suite against a high-level fault model
    Das, S
    Banerjee, A
    Basu, P
    Dasgupta, P
    Chakrabarti, PP
    Mohan, CR
    Fix, L
    18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 201 - 206
  • [5] On the use of a high-level fault model to analyze logical consequence of properties
    Brait, S
    Fummi, F
    Pravadelli, G
    THIRD ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2005, : 221 - 230
  • [6] Search-space optimizations for high-level ATPG
    Campos, Jorge
    Al-Asaad, Hussain
    MTV 2005: SIXTH INTERNATIONAL WORKSHOP ON MICROPRESSOR TEST AND VERIFICATION: COMMON CHALLENGES AND SOLUTIONS, PROCEEDINGS, 2006, : 84 - +
  • [7] EFSM manipulation to increase high-level ATPG effectiveness
    Di Guglielmo, Giuseppe
    Fummi, Franco
    Marconcini, Cristina
    Pravadelli, Graziano
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 57 - +
  • [8] On the Fault Coverage of High-level Test Derivation Methods for Digital Circuits
    Lopez, Jorge
    Vinarsky, Evgeny
    Laputenko, Andrey
    2017 18TH INTERNATIONAL CONFERENCE OF YOUNG SPECIALISTS ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES (EDM), 2017, : 184 - 189
  • [9] Enhancing topological ATPG with high-level information and symbolic techniques
    Corno, F
    Patel, JH
    Rudnick, EM
    Reorda, MS
    Vietti, R
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 504 - 509
  • [10] Verbalization of high-level formal proofs
    Holland-Minkley, Amanda M.
    Barzilay, Regina
    Constable, Robert L.
    Proceedings of the National Conference on Artificial Intelligence, 1999, : 277 - 284
12345